1. Field of the Invention
The present invention relates to data transfer control of an information processing device and, more particularly, a direct memory access control system.
2. Description of the Background Art
In a conventional information processing device having a central processing unit, a main storage device and an I/O apparatus connected through a bus, when data transfer occurs with the I/O apparatus, the central processing unit issues an instruction to the I/O apparatus to execute processing of transferring information from the I/O apparatus to the main storage device through the bus.
In such a case, the central processing unit (CPU) should constantly monitor the I/O apparatus under its control to wait for the completion of the data transfer operation, so that load on the CPU might be increased to degrade performance of the system as a whole. In recent years, therefore, adopted for data transfer control is a direct memory access control system (hereinafter, also referred simply as a DMA) in which a main storage device is directly accessed from an I/O apparatus to transfer data without through a CPU.
Japanese Patent Laying-Open No. 2000-148661, Japanese Patent Laying-Open No. 11-085683 and Japanese Patent Laying-Open No. 06-161947 disclose the information processing devices adopting a DMA which enables high efficiency and improvement in performance of the system as a whole in data transfer to a main storage device.
On the other hand, as one I/O apparatus, a CAN (Controller Area Network) module has been drawing attention. A CAN module, which is mainly used for apparatus mounted on automobiles, is characterized in enabling information data communication having high reliability and safety.
It is a common practice for a conventional CAN module to have a structure in which a message received through a bus is stored in a message box as a memory embedded in the CAN module.
Therefore, adopted for a CPU is a system of directly accessing the message box from the CPU upon a notification of interruption when reception of a message is acknowledged in the CAN module. Since message information will be deleted once it is read by an access from the CPU, the structure in which transfer is made from a memory in the CAN module to a main storage device has not been adopted.
As described above, because the CPU adopts the system of directly accessing the memory in the CAN module, no reading from the CPU causes overwrite of the message box by a subsequently received message.
In addition, since in an access from the CAN module to the CPU, a received message is read through a low-speed peripheral bus, reading is executed at a very low speed.